Can your PCBs survive lead free processes?
Application Note AP304
A testing time for PCBs
The introduction of lead free soldering technology introduces a significant challenge in electronics manufacture. When considering PCB reliability it is worth remembering that the toughest challenge a PCB is likely to encounter during its design life is:
|
|
Why is lead free such a tough test?
Over the past decades the assembly process has gradually changed and evolved and over the years PCBs are exposed to more and longer duration periods of thermal stress prior to shipment as finished product.
1. Consider a simple hand soldered PTH board. Using a tin lead solder each assembled PTH joint is perhaps exposed to a few seconds of 200 degrees at the tip of a soldering iron.
2. Now add wave soldering to the process - as the board travels over the wave perhaps one or 2 seconds of exposure to 200 degree plus, and an associated pre heat to activate the flux.
3. Adding surface mount single sided adds a dual wave to the soldering process.
4.Double sided surface mount adds a reflow process and associated heat and cooling to the equation.
5. Add BGA to the scene and it is inevitable the board will be exposed to the occasional rework.
6. Now implement lead free and all the above temperatures are lifted from just over 215° degrees to 245-260° C. Exposure to these temperatures for the duration required for satisfactory soldering may cause extensive and irreparable damage to vias an posts - unless the boards materials, design and manufacturing process are suitably designed to ensure the boards are durable enough to tolerate these conditions.
These circumstances combined with smaller hole diameters and trace and via geometries mean it is now important to understand how the PCB will behave - and more importantly whether it will survive through this initial phase of its life.
Assembly profile simulation:
By running sample coupons
through a thermal profile similar to lead fee assembly, and designing
the coupons to emulate the typical hole / size and technology (PTH /
uvia / stacked via etc) boards may be suitably preconditioned prior to
long term reliability test.
Running the coupons through assembly simulation provides a much more
realistic preparation prior to accelerated life test than simply
exposing the boards to normal thermal cycle profiles.
Assembly simulation for non reliability critical boards.
Even in non critical situations where boards are designed for consumer or short term use, assembly simulation will determine if the boards can survive assembly and rework without suffering open circuits or poor interconnect as a result of the assembly process.
How can the thermal profile of assembly be simulated?
Using interconnect stress
test (IST) is a proven method for simulating the assembly process.
IST is carried out by first adding a test coupon on the PCB panel. The
coupon is designed to be a statistically valid test vehicle for the type
of board you are using. For instance the smallest widely used hole size
on your board is added to the coupon, ensuring there are a statistically
significant number of holes (typically 600-800) on the board for testing to be valid. The
coupon also incorporates accurately designed traces used for heating,
these heater traces are close to the outer layers to simulate the actual
thermal experience of a board as it goes through reflow. The
coupon is then subjected to the desired number of simulated reflow /
rework thermal profiles.
How are the coupons tested?
As the coupons are small it is possible to either have the assembly
simulation testing performed as a service, or if you have a large amount
of ongoing testing it may be preferable to invest in your own
system. However during the learning phase submitting coupons for
test is the preferred method for most companies.
What are the benefits of IST testing?
IST test is a proven
approved by IPC
TM-650 standards)
method for reliability test, it produces results in
1 day compared
to weeks (typically
40 days for traditional test methods), and importantly is able to
fully simulate the arduous conditions experienced by PCBs as they
journey through the assembly process. After assembly simulation IST is
able to run up to 200 thermal cycles in under 2 days. Studies have
proved results under IST have excellent correlation with traditional
methods. (Reference
to IPC TR485)
Where can I obtain test
coupon data?
A comprehensive package of test coupon data is available here.
The package is around 10Mb and contains all the information you need to
add IST test coupons to your PCB panels.
Download your IST reliability coupon data pack