PCB Reliability Test

Application notes

The Polar Application Note library includes a comprehensive resource of information on PCB reliability testing. Use the search engine below to locate your subject of interest.

Microsoft Powerpoint - some of the notes on this page are in Powerpoint format - if you do not have a copy you may download a FREE viewer here.

Rationale for IST test temperatures - Paul Reid - PWB Corp

White paper discussing PCB reliability testing over temperatures above and below Tg and the implications of RoHS compliant substrates. Includes a discussion on the merits of testing at negative temperatures compared to accelerated test above Tg.  

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Rationale for IST test temperatures - Paul Reid - PWB Corp

White paper discussing PCB reliability testing over temperatures above and below Tg and the implications of RoHS compliant substrates. Includes a discussion on the merits of testing at negative temperatures compared to accellerated test above Tg.  

Discussion on non functional pad removal, backdrilling and PCB reliability - Bill Birch - PWB Corp

If you are considering non functional pad removal, and / or back drilling to aid signal integrity, this application note will give you an overview of some of the advantages and disadvantages of these approaches with respect to reliability performance.

Introduction to accelerated PCB reliability test using Interconnect Stress Test. (Powerpoint presentation)

This new Powerpoint presentation introduces IST (interconnect stress test) as a proven fast economic alternative to traditional oven based test methods for PCB reliability test. IST is especially effective in qualifying the suitability of PCBs for lead free production processes.

A testing time for PCBs

The introduction of lead free soldering technology introduces a significant challenge in electronics manufacture.  When considering PCB reliability it is worth remembering that the toughest challenge a PCB is likely to encounter during its design life is the assembly process itself.
This application note discusses the issues associated with lead-free PCB manufacturing.

Many OEM, CEM and PCB fabricators are adopting Interconnect Stress Test ( IST) as the preferred method of PCB testing because of the savings in cost and time. IST costs less  to complete accelerated stress testing than many other methods, and, at the same time, is a more comprehensive test that is representative of the board reliability during assembly, rework, and the end use environments. This application note discusses IST as an objective and comprehensive test method with repeatable and reproducible results.