Minimizing the effects of vias
on signal integrity

DRAFT
AP185

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Minimising the effects of vias on signal integrity:

This application note presents a series of options on minimising the effects of vias on signal integrity, and whilst recognising that in some desings you may need to model test and simulate via performance, there are also very many more applications where taking some simple steps can reduce the effect of vias to a point where they have only a small or negligable effect on your design.

Minimising the number of vias

First and most obvious point is to note down the critical traces for signal integrity and ensure these are routed with the minimum number of vias possible.

Removing non functional pads

l is a ferromagneother words the skin-effect resistance on the upper (nickel plated) surface of the trace will be m

Blind and buried vias

t of the (cop

Backdrilling

t of the (cop

Employing microvias 

Sk

Nickher than thaper) core side. Additionally, copper's resistivity (at room temperature) is 1.7 x 10-8 ohm metre, that of nickel, over four times greater at 7 x 10-8 ohm metre.

Effects on reliability - backdrilling

t lowf the trace.acteristic impedance displayed. The Polar Controlled Impedance Test System provides compensat

Effects on reliability - removing non functional pads

 

Aion for this effect. Series loss may be distinguished from the case of a slightly tapered track by testing from both ends of the trace. In the case of series loss the impedance waveform will appear to have the same rising slope when tested from either end.)

Selective nickel platingating a pcb microstrip trace reduces the useful length of the trace by a factor of three.

The effect can be minimised by selective plating with nickel and gold, arranging that only pads and edge contacts of the circuit are plated


Polar Instruments Ltd
Design & Test tools for PCB Controlled Impedance & Signal Integrity

www.polarinstruments.com
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Tel: +44 1481 253081 Fax: +44 1481 252476


© Polar Instruments 2005. Polar Instruments pursues a policy of continuous improvement. The specifications in this document may therefore be changed without notice. All trademarks recognised. 

Disclaimer: The information provided in this application note is for guidance only and you are strongly recommended to refer to other sources and other signal integrity and pcb fabrication professionals before putting a design into practice.