|Stackup design system application notes|
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The Polar Application Note library includes a comprehensive resource of information on stackup design and build. Use the search engine below to locate your subject of interest.
Specifying in-line coupon layout with CGen Coupon Generator
The Polar CGen Coupon Generator includes coupon layout styles that accommodate GGB's SET2DIL Picoprobe; CGen allows for multiple reference and test traces to be arranged in-line to minimise the amount of usable panel consumed by the coupon. This note walks through rapid creation of space optimised insertion loss coupons.
|Is Controlled Impedance new to you? Then read this helpful booklet first...|
|Introduction to controlled impedance PCBs PDF
(586k) Ideal for color print or on screen viewing
Printer friendly black and white version PDF (256k)
|Introduction to the Stackup Design System.|
How is a PCB made and what effects impedance?
Version 2 Now revised and updated to include inner layer and lamination stages
Audience: Will interest you if you want to offer initial training on how PCB fabrication effects impedance, this presentation is valuable to technicians starting training in PCB fabrication, and new designers who need an initial insight into aspects of PCB fabrication. The note is also of interest to companies involved in assembling PCBs as it sheds some light on the processes a PCB undergoes before it is populated.
|Using the Stackup Design System.|
Professional documentation of low layer count stacks with Speedstack's Virtual Materials Mode
Easy switching between Speedstack's Material Library and Virtual Material modes provides a powerful "freehand" approach to building and experimenting with stackups, allowing you to combine real and virtual materials in the same stack.
Exploring "What-if" scenarios with Speedstack's Virtual Material Mode
The new Speedstack VMM allows you to experiment with stackup concepts (for example, to examine the effects of different trace widths or dielectric heights) without reference to a materials library. You can pass your completed stack concept to your fabricator for editing with available materials or, for more specialized applications, perform material allocation in house.
Using Speedflex to document a stack with coated and uncoated areas
In this note we demonstrate Speedstack's versatility, using the Speedflex Navigator to document a stackup where the board includes areas that are coated with photoresist and surface traces that remain exposed.
Documenting the press cycles in sequential
lamination/HDI with Speedflex
PowerPoint presentation (1MB)
A powerful tool for creating and and documenting flex-rigid PCB layer stackups, Speedflex for Speedstack is equally powerful at documenting the press cycles in sequential lamination/HDI.
Getting started with Speedstack Speedflex
With Speedflex OEM designers create accurate, efficient, fully documented flex-rigid PCB stackups in just a few minutes. Fabricators can quickly calculate the impact of substituting materials to improve manufacturability and reduce cost while maintaining the specified parameters and performance. In this application note we introduce Speedstack's Flex Navigator and briefly walk through the process of adding a flexible core to a pre-built stack.
|Jan 05 CircuiTree article & resources||
"Happy Thoughts" - Happy
Specifying controlled impedance & communicating stackups
1 View article: (Happy Thoughts)
2. Stack up file download (here) - can be viewed in SB200
3. Monte Carlo analysis - (requires a full
licence or licensed evaluation of Si8000m) - download (here)
Designer's guide for Printed Circuit Board tolerances
PCBs are made from materials that stretch, shrink, twist and bow. During fabrication laminates are exposed to high temperatures and pressures and many chemical processes; other variables – etch factor, board thickness and dielectric (Er) values must also be taken into account. With these in mind this note provides some general guidance on tolerances for PCBs.
stackups with Speedstack
With PCB manufacturing supply chains becoming longer, increasing in distance both in time and geography — and modern circuit board designs increasingly complex — there is now great potential for communication error between PCB procurement specialists, PCB field application engineers and front end teams. This note describes how Speedstack technical reports provide a flexible and high quality communication tool for PCB fabricators and brokers.
Verifying stack design with
PCB designers often wish to verify that the stack design to be sent to a PC fabrication company is manufacturable. Speedstack 2008, with its "Remake Stack with Autostack" facility, makes it easy for PCB designer and fabricator to share builds and verify that the stack can be realised with the fabricator's available materials.
stacks for lead-free builds with
A common challenge for PCB fabricators is taking an existing FR4 stack and redesigning it for lead- free builds. Speedstack 2008 offers a powerful and automatic solution to this tedious process. In this note we change the core and prepreg materials from standard FR4 to material with a higher performance with only a few mouse clicks.
How to check for resin starvation by using
the DRC Excess Resin test in Speedstack
Polar's Speedstack PCB Stackup Builder
incorporates a comprehensive Design Rules Check (DRC) function that
includes checks for symmetry, copper balance, minimum trace and gap
widths and excess resin, etc. Values for excess resin may be added to
the material libraries for prepregs. This application note discusses
how to calculate the excess resin value for the Polar Speedstack
Base thickness and
isolation dimension definitions - PowerPoint presentation
This short note provides a graphical explanation of base thickness, finished thickness and isolation distance as used in Speedstack.
Calculating dielectric height with
Speedstack is fully integrated with the Si8000 Controlled Impedance Quick Solver/Si9000 PCB Transmission Line Field Solver to allow easy addition of controlled impedance structures to layers in the stackup. The H Value (the effective height of a dielectric substrate after the pressing of the stack) calculation produces the dielectric heights required for the Polar SI8000/9000 field solvers.
SB200 - New from
v5.1 Symmetrical Build slashes stackup creation time in half
- PowerPoint presentation
The SB200 Symmetrical Build function provides dramatic reductions in stackup creation time. With just a few mouse clicks you can create a design-rule checked symmetrical stackup in minutes.
Offset stripline -
construction matters - PowerPoint presentation
Calculating impedance accurately on striplines depends on the relative positions of prepreg and core in the stack. This presentation explains graphically how to ensure your calculations are as accurate as possible.(Download)
Transferring controlled impedance parameters between the SB200 and the Si8000
The SB200 incorporates the facility to add controlled impedance structures to a layer in the stackup. Structure parameters may be copied to the Si8000 Quick Solver for processing (for example by the Si8000 Goal Seeking function) and calculated values pasted back to the SB200 for insertion into the stackup.
This application note outlines the process of exchanging controlled impedance parameters between the SB200 and the Si8000 to add a controlled impedance structure with the correct impedance value to a stackup layer.
Updating Si8000m to
interface with SB200a Professional Edition
The new SB200a Professional edition is designed to communicate and share layer stackup information with the Si8000m controlled impedance field solver. Together they form a powerful unified system for documentation and design of complex high speed PCB layer stackups and associated transmission line structures.
To realise communication between the two packages Si8000m existing customers need to update to Si8000 Version 3.00 or above. Version 3.xx includes the links between the two products and supports some additional typical impedance controlled structures for multiple dielectric stackups.
|Using the Speedstack Coupon Generator|
Introducing the Speedstack
The Speedstack Coupon Generator product will quickly and easily generate controlled impedance test coupons from existing Speedstack projects. Download this Introduction to the Coupon Generator (PDF).
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