


Signal integrity / PCB loss application notes


What's new? 

Operational notes for DeltaL waveform test settings The Polar Atlas insertion loss test system incorporates the DeltaL 2 Line and DeltaL 3 Line and DeltaL 4 test methods. All of the acquired TDT Delta L waveforms are used as part of the waveform evaluation so this note explains that particular care must be taken when choosing waveform test settings if unexpected behaviour is not to be induced. 

Dielectric constant and loss tangent – are they related? This note – for new PCB designers or PCB designers wanting to move into high speed design – explains in layman's terms how dielectric constant and loss tangent are related and the implications for PCB transmission line design. 

Setting the acquisition start point for Atlas DeltaL3 measurements The location of the waveforms in the Atlas display window is critical for getting good results from a measurement. This note shows how waveforms can be positioned correctly to ensure all parts of the waveform are acquired and processed. This note deals with DeltaL3 measurements but the principles apply to all Atlas measurements. 

Determining input parameters for Huray roughness with the Polar Si9000e The Polar Si9000e field solver offers the Huray, Hammerstad and Groisse models for predicting the additional attenuation due to surface roughness. This note by Bert Simonovich focuses on applying the Cannonball model to determine the input parameters needed for Huray roughness model in Si9000e using data provided solely by manufacturers' data sheets. 

Practical Method for Modeling Conductor Surface Roughness Using The Cannonball Stack Principle In this white paper by Bert Simonovich a practical method for modeling conductor roughness is explored. By using available data published in material data sheets alone, an equivalent multisphere model, based on cubic closepacking of equal spheres, also known as Cannonball Stack, is developed. 

Operational notes for DeltaL waveform test settings The Polar Atlas insertion loss test system incorporates the DeltaL 2 Line and DeltaL 3 Line test methods. All of the acquired TDT Delta L waveforms are used as part of the waveform evaluation so this note explains that particular care must be taken when choosing waveform test settings if unexpected 

Dielectric constant and loss tangent – are they related? This note – for new PCB designers or PCB designers wanting to move into high speed design – explains in layman's terms how dielectric constant and loss tangent are related and the implications for PCB transmission line design. 

Considering the effects of TDR pulse risetime on PCB impedance measurements This brief discussion notes that a PCB transmission line's characteristic impedance is an intrinsic property of the structure and hardly changes at all with frequency and explains why, if you are measuring characteristic impedance using TDR, the measurement is independent of TDR risetime. 

Introduction to insertion loss Typically, impedance control will be necessary on PCBs running in the 100MHz to 3GHz frequency range, where signal integrity will be significantly affected by signal reflections. Above these frequencies signal loss will be an increasing factor in signal integrity. This application note is an introduction to the cause and effect of insertion loss which becomes predominant as you push upwards from 3GHz. 


Determining input parameters for Huray roughness with the Polar Si9000e The Polar Si9000e field solver offers the Huray, Hammerstad and Groisse models for predicting the additional attenuation due to surface roughness. This note by Bert Simonovich focuses on applying the Cannonball model to determine the input parameters needed for Huray roughness model in Si9000e using data provided solely by manufacturers' data sheets. 

Modelling DeltaL insertion loss measurements with the Polar Si9000e The Si9000e models insertion loss on a wide range of PCB structures and stackups; the models are accurate boundary element field solved calculations of insertion loss that will correlate with a variety of insertion loss measurement techniques, this note briefly discusses modeling the sparameter loss characteristics of a PCB substrate measured with the DeltaL methodology. 

RIE loss / attenuation measurement method and PCB manufacture This application note provides a brief introduction to RIE (Root Impulse Energy) testing, one of 4 PCB material loss (attenuation) measurement methods shortly to be published by IPC. RIE testing is aimed at the PCB manufacturing shop floor to provide an easily deployed and relatively straightforward method of monitoring the high frequency performance of PCBs to ensure they stay within an acceptable loss budget. 

Vias, stubs and minimizing their visibility to high speed signals Many PCB designers wish to model plated through hole (PTH) vias with respect to impedance. However, from a signal integrity standpoint, unconnected via stubs have a far larger effect on the signal than the geometry of the via itself. This note explains how the Polar Si9000 can help you check if, at your desired bit rate or operating frequency, you need to take steps to reduce or remove the effects of via stubs. 

An introduction to forward and reverse crosstalk Crosstalk is the unwanted coupling of energy between two or more adjacent lines. The electromagnetic fields between two closely coupled lines interact with each other and will affect the behaviour of the signals on both lines. This note discusses near and farend crosstalk and includes formulas that will enable the maximum peak effect to be predicted. 

Nickelgold plating copper PCB traces Nickel plating of copper PCB traces, widely practised in the microwave industry, is acceptable on short lengths of pad to accommodate gold plating; plating the whole trace length is generally not a good idea. This application note explains the effect that nickel will have on high frequency transmission lines. 

Locating Critical Tracks on PCB Inner Layers From susceptibility to electrical interference to control of track crosssectional dimensions — this note provides several good reasons why you shouldn’t put critical tracks on the surface layer of a PCB. 

Transmission line testing – VNA or TDR? Sometimes board fabricators are asked to test PCB transmission lines at a given frequency. In some cases boards are tested using a Vector Network Analyser (VNA) and in others a Time Domain Reflectometer (TDR); both instruments should offer similar readings. This note sets out to explain expected differences in measurement results, and points out where differences are due to incorrect test setup rather than any material problem. 

Rounding loss tangent leads to large modeling errors Because Loss Tangent (TanD) is a small number it is sometimes tempting to round it off to fewer decimal places, dismissing the numbers far to the right of the decimal point. However, this can lead to unintended miscalculations when rounding small value parameters such as Loss Tangent which has a directly proportional effect on the insertion loss. 

Using the Si9000 Loss Tangent Goal Seek Measuring insertion loss yields the total losses of a transmission line, but sometimes it is useful to further process that information and deduce the contribution of copper losses and dielectric losses to the overall loss figure. The Si9000e Loss Tangent Goal Seek provides a useful estimate of the dielectric loss tangent for the substrate material. This application note describes the sequence of steps to goal seek for loss tangent. 


Modelling DeltaL insertion loss measurements with the Polar Si9000e The Si9000e models insertion loss on a wide range of PCB structures and stackups; the models are accurate boundary element field solved calculations of insertion loss that will correlate with a variety of insertion loss measurement techniques, this note briefly discusses modeling the sparameter loss characteristics of a PCB substrate measured with the DeltaL methodology. 

Impedance variation with frequency can be counter intuitive! Although transmission line impedance is broadly constant over a wide range of frequencies, as the dielectric constant of a PCB transmission line tends to fall slightly with increasing frequency you might anticipate that Z_{0} would increase as you sweep through the frequency range. A quick calculation with a range of frequencies in the Si9000e transmission line field solver shows this is not the case. This application note explains why… 

Using the Si9000e's sensitivity analysis to graph multiple impedances Some transmission system guidelines specify routing signals with constraints on both differential impedance and common impedance. This note describes how to use the Si9000e's sensitivity analysis to achieve both the differential (Zdiff) and common (Zcommon) impedance specifications. 

Using the Si9000e's sensitivity analysis to graph crosstalk The Si9000e's sensitivity analysis includes graphing for differential, common, odd and even mode impedances along with near and farend crosstalk. This note describes how you can use the Si9000e's sensitivity analysis to graph the effect on crosstalk (NEXT and FEXT) of changing both the separation, S1, and trace width, W1 and W2, of a differential pair while maintaining constant impedance. 

AP8184 
Si9000 frequency dependent calculations Causal interpolation of dielectric constant is implemented in the Si9000e lossy line field solver via the Extended Substrate Data option. Using the Extended Substrate Data option the Si9000 can accept tables of multiple values of dielectric constant and loss tangent or use a single value to enable SvenssonDjordjevic frequency dependent permittivity modelling. 

Choosing appropriate configuration parameters for the Si8000/Si9000's sensitivity analysis The Sensitivity Analysis tab of the Si8000m and Si9000e field solvers allows you to graph the effect of a range of changing parameter values. This note demonstrates the effects of changing the upper substrate height for a range of trace widths and shows how it is sometimes necessary to change the ConfigurationParameters minimum and maximum values to ensure they are appropriate for the selected structure. 

Laminates, losses & the Si9000e – choosing a PCB laminate New "mid market" core and prepreg materials offer increased high speed performance and more standard processing methods than more exoticlaminates and have presented the designer with a bewildering array of choices from ease of processing through to reliability requirements and onwards to signal integrity capability. This note explains how to use the Si9000e to make the best choice of laminate materials when trading cost versus signal integrity performance. 

Surface roughness effect on PCB trace attenuation / loss Designers and fabricators are increasingly concerned with the effects on PCB transmission line losses of the surface roughness of the copper layers within a stackup. With the Si9000 versions 9.01 and above you can include values for surface roughness in frequency dependent calculations. Charting dielectric losses along with conductor losses and attenuation values that include compensation for surface roughness can help isolate the contributions of the different loss mechanisms. 

Modelling and testing broadsidecoupled differential pairs without ground From a modelling standpoint the broadsidecoupled differential pair without ground is like a paired wire transmission line. This structure does not appear directly in the Si8000/9000 field solver; this application note discusses how to use one of the standard Si8000/9000 structures to predict the finished impedance and suggests a method of testing for this differential structure. 

Modelling and testing differential pairs without ground From a modelling standpoint the differential pair without ground is like a paired wire transmission line. Although this structure does not appear in the Si8000/9000 field solver this note shows how to use one of the standard Si8000/9000 structures to predict the finished impedance and suggests a method of testing for this differential structure. 

Displaying sparameters with Smith charts on the Si9000 The Si9000 v7 and later allows graphical representation of sparameters S_{11} and S_{21} via a Smith Chart, a tool widely used for graphic solution of transmissionline networks. This note briefly discusses how reflection and transmission coefficients S_{11} and S_{21} of a typical 50 Ohm controlled impedance structure, represented as a transmission line, are graphed by the Si9000. 

Ground plane thickness in Si9000 frequency dependent calculations This application note describes how the Si9000 PCB Transmission Line Field Solver fully takes into consideration power plane thickness in frequency dependent calculations. 

Introduction to sparameters The Si9000 extracts RLGC matrices and 2Port (singleended) or 4Port (differential) sparameters and rapidly plots transmission line information for the structure under design. This application note provides a simple introduction to the concepts of sparameters, or scattering parameters, which describe the "scattering", reflection and transmission of travelling waves when a linear network is inserted into a transmission line. PowerPoint presentation. Right click the link, then choose "Save Target As..." to download. Download free Powerpoint viewer. 

Polar recommended signal integrity reading For those who would like more information on signal integrity issues, this note contains a list of books recommended by Polar. 

Critical length of transmission lines  Dr. Eric Bogatin This application note gives a clear and easy to read explanation of the critical length of a transmission line. Written for Polar by Dr. Eric Bogatin this article is an ideal place to broaden your knowledge of PCB transmission line behaviour. If you like this you will also find a broad range of PCB signal integrity related training materials on the Bogatin Enterprises website. www.bogent.com 

Effect of risetime on the TDR measurement of impedance This application note is intended to give guidance to those making impedance measurements on industry standard 6 inch long coupons. The note will show that in this situation the use of risetimes shorter than 200ps will yield no advantage and in fact may prove more difficult to use. 

Setting the acquisition start point for Atlas DeltaL3 measurements The location of the waveforms in the Atlas display window is critical for getting good results from a measurement. This note shows how waveforms can be positioned correctly to ensure all parts of the waveform are acquired and processed. This note deals with DeltaL3 measurements but the principles apply to all Atlas measurements. 

Specifying the timebase and line length settings for Atlas DeltaL tests Polar's Atlas PCB insertion loss test sytem includes the DeltaL technique which uses long line short line measurement combined with innovative via deembedding techniques. This note discusses the test parameter settings to ensure best results over a range of test line lengths. 

Insertion loss testing frequently asked questions Frequently asked questions on insertion loss testing with Polar Atlas using SET2DIL and SET2SEIL. 

Atlas insertion loss correlation study This insertion loss correlation study assesses the correlation between the following single ended and differential test methods and modelling techniques, Vector Network Analyser, SPP (Short Pulse Propagation) test method, SET2DIL (Single Ended TDR to Differential Insertion Loss) / SET2SEIL (Single Ended TDR to Single Ended Insertion Loss) and Polar Instruments Si9000e Insertion loss GHz PCB transmission line field solver. 

Si9000e – Atlas modeled v measured insertion loss correlation study The Si9000e – ATLAS Modeled v Measured Insertion Loss Correlation Study assesses the correlation between insertion losses predicted by the Si9000e transmission line field solver and the attendant test results obtained from single ended and differential test methods Vector Network Analyser, SPP (Short Pulse Propagation) test method, SET2DIL (Single Ended TDR to Differential Insertion Loss) / SET2SEIL (Single Ended TDR to Single Ended Insertion Loss.) 